View ASM2I2310AG-24TR_284834.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

November 2006 rev 0.3 2.5-V TO 3.3-V High-Performance Clock Buffer
Features
* High-Performance 1:10 Clock Driver for General Purpose applications. Operates up to 200 MHz at 3.3V Supply Voltage * Pin-to-Pin Skew < 100 pS at 3.3V Supply Voltage * Supply Range : 2.3V to 3.6V * Operating Temperature Range : -40C to 85C * Output Enable Glitch Suppression * Distributes One Clock Input to Two Banks of Five Outputs * 25 On Chip Series Damping Resistors * Packaged in 24 Pin TSSOP Package
ASM2P2310A
Product Description
The ASM2P2310A is a high-performance, low-skew clock buffer that operates up to 200MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5V and 3.3V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals. The ASM2P2310A is characterized for operation from -40C to 85C.
Block Diagram
CLK
24
3 25
1Y0
21 25
2Y0
4 25
1Y1
20 25
2Y1
5 25
1Y2
17 25
2Y2
8 25
1Y3
16 25
2Y3
9 1G 11 25 LOGIC CONTROL
1Y4 2G 13 LOGIC CONTROL
12 25
2Y4
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006 rev 0.3
Pin Configuration
GND VDD 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VDD 1G 2Y4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 CLK VDD VDD 2Y0 2Y1 GND GND 2Y2 2Y3 VDD VDD 2G
ASM2P2310A
ASM2P2310A 19
18 17 16 15 14 13
Pin Description Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
GND VDD 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VDD 1G 2Y4 2G VDD VDD 2Y3 2Y2 GND GND 2Y1 2Y0 VDD VDD CLK
Type
P P O O O P P O O P I O I P P O O P P O O P P I Ground Pin DC Power supply, 2.3 V - 3.6V Buffered Output Clock Buffered Output Clock Buffered Output Clock Ground Pin Ground Pin Buffered Output Clock Buffered Output Clock
Description
DC power supply, 2.3V - 3.6V Output enable control for 1Y[0:4] outputs. meaning the 1Y[0:4] clock outputs follow the high. Buffered Output Clock Output enable control for 2Y[0:4] outputs. meaning the 2Y[0:4] clock outputs follow the high. DC power supply, 2.3V - 3.6V DC power supply, 2.3V - 3.6V Buffered Output Clock Buffered Output Clock Ground Pin Ground Pin Buffered Output Clock Buffered Output Clock DC power supply, 2.3V - 3.6V DC power supply, 2.3V - 3.6V Input reference frequency
This output enable is active-high, input clock (CLK) if this pin is logic
This output enable is active-high, input clock (CLK) if this pin is logic
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
2 of 11
November 2006 rev 0.3
Function Table Input 2G
L L H H
ASM2P2310A
Output CLK

1G
L H L H
1Y[0:4]
L CLK L CLK1
1
2Y[0:4]
L L CLK1 CLK1
Note: 1 After detecting one negative edge on the CLK input, the output follows the input CLK if the control pin is held high.
Detailed Description Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the input clock) (see Figure 1). The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for predictable operation.
CLK
Gn
Yn tsu(en) th(en)
a) Enable Mode
CLK
Gn
Yn tsu(dis) th(dis)
b) Disable Mode Figure 1. Enable and Disable Mode Relative to CLK
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
3 of 11
November 2006 rev 0.3
Absolute Maximum Ratings Parameter
Supply Voltage range, VDD Input Voltage range, VI
1,2
ASM2P2310A
Rating
-0.5V to 4.6V -0.5 V to VDD + 0.5 V -0.5 V to VDD + 0.5 V 50 mA 120C/W -65C to 150C 2KV
Output Voltage range, VO1,2 Continuous total output current, IO (VO = 0 to VDD) Package thermal impedance, JA3: PW package Storage temperature range Tstg Static Discharge Voltage , tDV (As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Notes : 1 The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2 This value is limited to 4.6 V maximum. 3 The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions1 Parameter
Supply voltage, VDD Low-level input voltage, VIL High-level input voltage, VIH Input voltage, VI High-level output current, IOH Low-level output current, IOL VDD = 3V to 3.6V VDD = 2.3 V to 2.7V VDD = 3V to 3.6V VDD = 2.3V to 2.7V -40 VDD = 3V to 3.6V VDD = 2.3V to 2.7V VDD = 3V to 3.6V VDD = 2.3V to 2.7V 2 1.7 0 VDD 12 6 12 6 85
Min
2.3
Typ
2.5 3.3
Max
3.6 0.8 0.7
Unit
V V V V mA mA C
Operating free-air temperature, TA
Note:1 Unused inputs must be held high or low to prevent them from floating.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
4 of 11
November 2006 rev 0.3
Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
ASM2P2310A
Symbol
VIK II IDD2 CI CO
Parameter
Input voltage Input current Static device current Input capacitance Output capacitance VDD = 3V, VI = 0V or VDD
Test Conditions
II = -18 mA IO = 0 mA VI = 0V or VDD VI = 0V or VDD
Min
Typ1
Max
-1.2 5 80
Unit
V A A pF pF
CLK = 0V or VDD, VDD = 2.3V to 3.6V, VDD = 2.3V to 3.6V,
2.5 2.8
Note: 1 All typical values are at respective nominal VDD. 2 For ICC over frequency, see Figure 6.
VDD = 3.3 V 0.3 V Symbol
VOH
Parameter
High-level output voltage
Test Conditions
VDD = Min to Max, VDD = 3 V IOH = -100 A IOH = -12 mA IOH = -6 mA IOL = -100 A IOL = 12mA IOL = 6 mA VO = 1V VO = 1.65V VO = 3.135V VO = 1.95V VO = 1.65V VO = 0.4V
Min
VDD - 0.2 2.1 2.4
Typ1
Max
Unit
V
VDD = Min to Max, VOL Low-level output voltage VDD = 3V VDD = 3V, IOH High-level output current VDD = 3.3V, VDD = 3.6V, VDD = 3V, IOL Low-level output current VDD = 3.3V, VDD = 3.6V,
Note: 1 All typical values are at respective nominal VDD.
0.2 0.8 0.55 -28 -36 -14 28 36 14 mA mA V
VDD = 2.5 V 0.2 V Symbol
VOH VOL
Parameter
High-level output voltage Low-level output voltage
Test Conditions
VDD = Min to Max, VDD = 2.3V VDD = Min to Max, VDD = 2.3V VDD = 2.3V, VDD = 2.5V, VDD = 2.7V, VDD = 2.3V, IOH = -100 A IOH = -6 mA IOL = 100 A IOL = 6 mA VO = 1V VO = 1.25V VO = 2.375V VO = 1.2V VO = 1.25V VO = 0.3V
Min
VDD - 0.2 1.8
Typ1
Max
Unit
V
0.2 0.55 -17 -25 -10 17 25 10
V
IOH
High-level output current
mA
IOL
Low-level output current
VDD = 2.5V, VDD = 2.7V,
mA
Note: 1 All typical values are at respective nominal VDD.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
5 of 11
November 2006 rev 0.3
Timing Requirements
Over recommended ranges of supply voltage and operating free-air temperature
ASM2P2310A
Symbol
fclk
Parameter
Clock frequency
Test Conditions
VDD = 3 V to 3.6V VDD = 2.3 V to 2.7V
Min
0 0
Typ
Max
200 170
Unit
MHz
Switching Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
VDD = 3.3 V 0.3 V (See Figure 2) Symbol
tPLH tPHL tsk(o) tsk(p) tsk(pp) tr tf tsu(en) tsu(dis) th(en) th(dis)
Parameter
CLK to Yn Output skew (Ym to Yn)1(see Figure 4) Pulse skew (see Figure 5) Part-to-part skew Rise time (see Figure 3) Fall time (see Figure 3) Enable setup time,G_high before CLK Disable setup time, G_low before CLK Enable hold time, G_high after CLK Disable hold time, G_low after CLK
Test Conditions
f = 0 MHz to 200 MHz For circuit load, see Figure 2.
Min
1.3
Typ
Max
2.8 100 250 500
Unit
nS pS pS pS V/nS V/nS nS nS nS nS
VO = 0.4V to 2V VO = 2 V to 0.4V
0.7 0.7 0.1 0.1 0.4 0.4
2 2
Note: 1 The tsk(o) specification is only valid for equal loading of all outputs
VDD = 2.5 V 0.2 V (See Figure 2) Symbol
tPLH
Parameter
CLK to Yn
Test Conditions
f = 0MHz to 170MHz For circuit load, see Figure 2.
Min
1.5
Typ
Max
3.5 170 400 600
Unit
nS pS pS pS V/nS V/nS nS nS nS nS
tPHL tsk(o) tsk(p) tsk(pp) tr tf tsu(en tsu(dis) th(en) th(dis)
1 Output skew (Ym to Yn) (see Figure 4)
Pulse skew (see Figure 5) Part-to-part skew Rise time (see Figure 3) Fall time (see Figure 3) Enable setup time,G_high before CLK Disable setup time, G_low before CLK Enable hold time, G_high after CLK Disable hold time, G_low after CLK VO = 0.4V to 1.7V VO = 1.7V to 0.4V 0.5 0.5 0.1 0.1 0.4 0.4
1.4 1.4
Note: 1 The tsk(o) specification is only valid for equal loading of all outputs.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
6 of 11
November 2006 rev 0.3
Parameter Measurement Information
From Output Under Test CL = 25 pF on Yn 500
ASM2P2310A
A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR 200 MHz, ZO = 50, tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
VDD CLK 50% VDD 0V tPLH tPHL VOH 50% VDD 0.4V tr tf 0.4V VOL
1.7V or 2V Yn
Figure 3. Voltage Waveforms Propagation Delay Times
VDD CLK 0V VOH Any Y 50% VDD VOL
VOH Any Y 50% VDD VOL tSK(O) tSK(O)
Figure 4. Output Skew
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
7 of 11
November 2006 rev 0.3
ASM2P2310A
VDD CLK 50% VDD 0V tPLH Yn NOTE: tsk(p) = | tPLH - tPHL | 50% VDD VOL tPHL VOH
Figure 5. Pulse Skew
SUPPLY CURRENT vs FREQUENCY
f - Frequency - MHz Figure 6.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
8 of 11
November 2006 rev 0.3
Package Information 24L TSSOP (173 mil)
ASM2P2310A
Dimensions Symbol
A A1 A2 D L E E1 R R1 b c L1 e
Inches Min Max
.... 0.0020 0.031 0.3031 0.020 0.169 0.004 0.004 0.007 0.004 0.043 0.0059 0.041 0.311 0.030 0.177 .... .... 0.012 0.008
Millimeters Min Max
... 0.05 0.80 7.70 0.50 4.30 0.09 0.09 0.19 0.09 1.2 0.15 1.05 7.90 0.75 4.50 ..... ..... 0.30 0.20
0.252 BSC
6.40 BSC
0.039 REF 0.026 BSC 0 8 0
1.0 REF 0.65 BSC 8
a
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
9 of 11
November 2006 rev 0.3
Ordering Information Part Number
ASM2P2310AF-24TR ASM2P2310AF-24TT ASM2P2310AG-24TR ASM2P2310AG-24TT ASM2I2310AF-24TR ASM2I2310AF-24TT ASM2I2310AG-24TR ASM2I2310AG-24TT
ASM2P2310A
Marking
2P2310AF 2P2310AF 2P2310AG 2P2310AG 2I2310AF 2I2310AF 2I2310AG 2I2310AG
Package Type
24-Pin TSSOP, TAPE & REEL, Pb Free 24-Pin TSSOP, TUBE, Pb Free 24-Pin TSSOP, TAPE & REEL, Green 24-Pin TSSOP, TUBE, Green 24-Pin TSSOP, TAPE & REEL, Pb Free 24-Pin TSSOP, TUBE, Pb Free 24-Pin TSSOP, TAPE & REEL, Green 24-Pin TSSOP, TUBE, Green
Temperature
Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial
Device Ordering Information
ASM2P2310A
F-24
TR
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent Nos 5,488,627 and 5,631,920.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
10 of 11
November 2006 rev 0.3
ASM2P2310A
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: ASM2P2310A Document Version: v0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
11 of 11

▲Up To Search▲

Price & Availability of ASM2I2310AG-24TR

	To Download ASM2I2310AG-24TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .